Its a pleasure to talk to Dr. Walden (Wally) C. Rhines, chairman and CEO, Mentor Graphics Corp. On his way to DAC 2013, where he will be giving a ten-minute "Visionary Talk", he found time to speak with me. First, I asked him given that the global semiconductor industry is entering the sub-20nm era, will it continue to be ‘business as usual’ or ‘it’s going to be different this time’?
Dr. Rhines said: "Every generation has some differences, even though it usually seems like we’ve seen all this before. The primary change that comes with “sub-20nm” is the change in transistor structure to FinFET. This will give designers a boost toward achieving lower power. However, compared to 28nm, there will be a wafer cost penalty to pay for the additional process complexity that also includes two additional levels of resolution enhancement."
Impact of new transistor structures
How will the new transistor structures impact on design and manufacturing?
According to him, the relatively easy impact on design is related to the simulation of a new device structure; models have already been developed and characterized but will be continuously updated until the processes are stable. More complex are the requirements for place and route and verification; support for “fin grids” and new routing and placement rules has already been implemented by the leading place and route suppliers.
He added: "Most complex is test; FinFET will require transistor-level (or “cell-aware”) design for test to detect failures, rather than just the traditional gate-level stuck-at fault models. Initial results suggest that failure to move to cell-aware ATPG will result in 500 to 1000 DPM parts being shipped to customers.
"Fortunately, “cell-aware” ATPG design tools have been available for about a year and are easily implemented with no additional EDA cost. Finally, there will be manufacturing challenges but, like all manufacturing challenges, they will be attacked, analyzed and resolved as we ramp up more volume."
Introducing 450mm wafer handling and new lithography
Is it possible to introduce 450mm wafer handling and new lithography successfully at this point in time?
"Yes, of course," Dr. Rhines said. "However, there are a limited number of companies that have the volume of demand to justify the investment. The wafer diameter transition decision is always a difficult one for the semiconductor manufacturing equipment companies because it is so costly and it requires a minimum volume of machines for a payback. In this case, it will happen. The base of semiconductor manufacturing equipment companies is becoming very concentrated and most of the large ones need the 450mm capability."
What will be the impact of transistor variability and other physics issues?
As per Dr. Rhines, the impact should be significant. FinFET, for example requires controlling physical characteristics of multiple fins within a narrow range of variability. As geometries shrink, small variations become big percentages. New design challenges are always interesting for engineers but the problems will be overcome relatively quickly.
Will Moore's Law keep on track?
Will the new technological advances deliver the cost and performance advantages to keep Moore’s Law on track?
He said: "It looks like Moore’s Law is good for 14nm, and probably, 10nm. However, the overarching driving force is the learning curve. Moore’s Law is just a special case of the learning curve where most cost reduction is achieved by shrinking feature sizes and increasing wafer diameters. Somewhere in the not too distant future (probably with 14/16/20nm technology) we stop gaining the 30 percent per year cost reduction benefit of shrinking feature sizes on a Moore’s Law trend; at that point, continuing on the learning curve requires innovation in other areas such as 3D structures."
Moore’s Law is a 50-year phenomenon; the broader law of the learning curve lasts for centuries, maybe forever. Cost reductions from the learning curve are driven by growth of unit volume; fortunately the growth in unit volume of transistors continues to be about 70 percent per year, an order of magnitude or more larger than most commodities. This continuing cost reduction is what makes the semiconductor industry such an exciting place to be.
Future opportunities for 2.5/3D ICs
Let us also look at the future opportunities for 2.5/3D ICs.
According to Dr. Rhines: "Memory provides the biggest near term impact; while we aren’t at cost per bit parity yet, the manufacturing capability for DRAM and FLASH stacks is well defined. Logic and mixed signal are beginning to move to hybrid structures on interposers as cost and performance capabilities demand. Power and performance will lead to microprocessors with memories on top via wide I/O busses on more and more applications. Multi-die stacked logic die connected by TSV’s are farther into the future."
Finally, what are the best solutions to the wafer thinning requirements for power devices and 2.5/3D ICs?
He said that for 2.5/3D devices, there are manufacturing processes that are already in volume production for products like image sensors. (Dr. Rhines actually worked on these processes in the 1970s when they produced thinned CCD’s on 25 micron thick silicon for special applications).
The technology for TSV’s and associated chip handling for interposer-based products is not as mature but it’s only a matter of time and yield as these mature. Both, multi-die memory stacks and multi-chip functions on interposers (probably non-silicon interposers) will become increasingly prevalent, he concluded.